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It is included in the 2024 version of UDE, the company’s universal debug engine.
With UDE “the Cortex-R52 main cores and the Cortex-M7 auxiliary cores are all visible and can be controlled from one common debugger user interface”, according to PLS. “This eliminates the need to open separate debugger instances for each core. The debugger user interface can be customised to meet specific requirements and naturally supports multiscreen operation.”
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Configurable perspectives allow multiple views to be defined for particular debugging tasks, and there are predefined configurations for the S32N55.
Subsets of the cores can be synchronised, or synchronisation can be disabled. By default, all S32N55 cores belong to a run control group, and are synchronised for run control, and breakpoints and single steps work on all cores, regardless of which core hits the breakpoint or for which core the single steps are executed.
“Especially for applications where tasks are distributed across multiple cores and shared code is used, UDE’s multicore breakpoint feature significantly eases debugging,” claimed PLS. “A multicore breakpoint is effective regardless of which core is currently executing the specific code.”
For non-invasive multicore debugging and run-time analysis, features based on recorded information from Arm’s CoreSight trace system – included in S32N55 – are available. These include profiling, call graph analysis and code coverage.
For external recording of S32N55 trace data – transferred from the chip to via a parallel interface – PLS offers two hardware units: UAD2next with 512Mbyte of trace memory or UAD3+ (pictured) with up to 4Gbyte. Or the trace can be captured in on-chip memory and downloaded via SWD (serial wire debug) after recording.
S32N55 ?
S32N55 has 16 Arm Cortex-R52 real-time processor cores, is made on a 5nm automotive-qualified process, and is capable of supporting ISO 26262 ASIL D functional safety, according to PLS.
It is aimed at central vehicle control units that consolidate the functions of multiple separate vehicle ECUs (electronic control units), possibly including legacy code from earlier vehicles. As such, it has hardware virtualisation to deterministically prevent multiple operating systems and other code blocks from interacting – inhibiting the spread of faults and hacking.
Find PLS in hall 4 on stand 310 at Embedded World 2024.
