FPGA / PLD

Lattice has switched to 28nm FD-SOI (fully-depleted silicon-on-insulator) technology for a range of sram-based FPGAs intended for embedded vision and artificial intelligence processing in industrial, automotive and consumer systems. Although they are ram-based, and therefore need to boot from adjacent memory, the firm has found a way to get chip outputs enabled, set and stable within 3ms of power-up – allowing ...

The working practices of today’s young engineers are very much on Victor Peng’s mind. The president and CEO of Xilinx explained why the company’s Vitis, the software platform announced at the Xilinx Developers’ Forum in San Jose, California. He conceded that the company has not normally been associated with open source products. Now it is offering Vitis. “The new generation ...

Microchip detailed an FPGA family with a quad core 64bit RISC-V processor alongside the programmable array. Called ‘PolarFire SoC’, the “architecture brings real-time deterministic asymmetric multiprocessing capability to Linux platforms in a multi-core coherent CPU cluster”, according to the firm, which worked with Risc-V specialist SiFive to create the devices. Real-time operation is included for safety-critical, system control and trusted ...

Xilinx embraces open source community and introduces the Vitis software platform for hardware and software development. At this year’s Xilinx Developers Forum, the company introduced the Vitis software platform, which tailors the hardware architecture to the software of algorithm code without intervention. President and CEO, Victor Peng, explained that the unified platform was developed to “empower software developers, with the ...

Intel is shipping Stratix 10 DX FPGAs which are designed to support Intel Ultra Path Interconnect (Intel UPI), PCI-Express (PCIe) Gen4 x16, and a controller for Intel Optane memory to provide acceleration. Stratix 10 DX FPGAs with the new interfaces include the option to support select Intel Optane DC persistent memory DIMMs. They  increase bandwidth and provide coherent memory expansion and ...

Aldec improves its HES Proto-AXI software to provide greater support hardware verification and software validation.

Intel begins shipments of the first Agilex FPGAs to early access program customers.

The RISC-V Summit was held in Santa Clara, California, USA this week (3 – 6 December). The industry looked ahead to the potential of the open architecture and was a platform for the providers of core IP and development tools that make up its ecosystem. There were two announcements from IAR Systems in support of establishing a robust ecosystem for ...

Xilinx Developer Forum: Claimed to be the highest performance convolutional neural network (CNN) on an fpga, Omnitek’s CNN is available now. The deep learning processing unit (DPU) is future-proofed, explained CEO Roger Fawcett, due to the programmability of the fpga. It was demonstrated as a GoogLeNet Inception-v1 CNN, using eight-bit integer resolution. It achieved 16.8 terra operations per second (TOPS) ...

Two accelerator cards, the Alveo U200 and Alveo U250, announced by Xilinx, improve latency rates