Tag Archives: EDA tools

Nicomatic has contracted SnapEDA to provide CAD models for two-row versions of Nicomatic’s CMM 220 and 320 micro connector series – a total of over eight million variants. “Options range from 4 to 60 for signal contacts and 4 to 54 for coaxial or power contacts with locking or racking fixings,” according to SnapEDA. “To generate the parts, engineers need ...

Risk-V intellectual property company Andes Technology has certified simulation reference models from Imperas reference for use evaluating multi-core designs featuring the functional-safety-optimised AndesCore N25F-SE. At the same time, it also certified the complete range of Andes processor IP blocks with ‘Andes Custom Extension’ (ACE) support. Such virtual references run exactly the same binary code as any resulting hardware would. “Functional ...

Cadence has announced a design tool for IC design sign-off. Called Certus closure solution, the “environment automates and accelerates the complete design closure cycle, from sign-off optimisation through routing, static timing analysis and extraction”, said Cadence. “The solution supports the largest chip design projects with unlimited capacity.” It lists these attributes: Distributed hierarchical optimisation and sign-off architecture for cloud and ...

Synopsys has unified the workflow through its existing reliability analysis tools for analogue, mixed-signal and custom IC designs – integrating them into its PrimeWave design environment, along with PrimeSim Continuum that announced in April. The unified workflow is to be called PrimeSim Reliability Analysism and is an umbrella for its CKK, Custom Fault, AVA, SPRES, EMIR and  MOSRA tools (see table ...

Microchip has released a C++ algorithm high-level synthesis design workflow for its PolarFire FPGAs. “A large majority of edge compute, computer vision and industrial control algorithms are developed natively in C++ by developers with little or no knowledge of underlying FPGA hardware,” according to the company. Called SmartHLS, the tool allows C++ algorithms to be directly translated to FPGA-optimised RTL ...

Risc-V core design house Andes Technology has certified reference models for its cores with ‘P’ extensions from Imperas. Cores carrying the P designation have SIMD and DSP extensions to the instruction set for data processing and real-time operation. “The RISC-V International P Extension Task Group is in the final stages of submitting the specification to the official ratification process, which ...

Chip foundry X-Fab has announced a reference design kit for its XH018 180nm modular mixed-signal high-voltage CMOS process and Siemens’ Tanner analogue and mixed-signal (AMS) EDA software. “The kit is based on silicon-proven circuitry, providing coverage of the flow to design and simulate analogue and mixed-signal ICs,” according to X-Fab which “provides its customers reference design flows based on its established ...

Claiming to be able to reduce design compile times by a factor of five, Xilinx has launched the Vivado ML Editions tool suite. The latest addition to the company’s Vivado tool suite is believed to be the first FPGA EDA tool suite based on machine learning (ML) optimisation algorithms. In addition to faster compile times, it is claimed to deliver ...

JEP181 from JEDEC is a neutral file XML-based standard for thermal models. The chosen file format is ECXML, for ‘electronics cooling extensible mark-up language’. “A de facto standard for a number of years, ECXML is now published by JEDEC as the JEP181 guideline,” according to Siemens, which participated in the creation of the standard. “The standard was created to meet a ...

Cadence has announced its next generation of emulation and prototyping hardware. Both aimed at of multi-billion-gate SoC designs, Palladium Z2 Enterprise Emulation is for pre-silicon hardware debug, and Protium X2 Enterprise Prototyping is for pre-silicon software validation. They follow on from Palladium Z1 and Protium X1. Based on Xilinx UltraScale+ VU19P FPGAs, “these systems provide customers with 2x capacity and 1.5x ...