Intellectual property rights are still taking a beating in China
EDA and IP
Cadence expands VC programme
The EDA firm is bringing its two venture capital assistance schemes to Europe and to China
Crolles2 expands into IP development
Chip alliance between Freescale, Philips and ST agrees to work on intellectual property
Mosfet model raises accuracy
Advanced Mosfet model provides more accurate device behaviours down to 45nm
EDA revenue sees 3% rise
Design automation industry grew just three per cent in 2004
Atrenta goes floorplanning
Ambitious plan to extend firm's product roadmap into chip level planning and implementation
Initiative cuts 90nm power by 40%
Industry collaboration makes significant power savings on 90 nanometre ARM processor design
Network-on-chip tools replace bus
Arteris unveils tools that implement network-on-chip technology to replace conventional bus structures
End of point tools, says de Geus
The chairman and chief executive of Synopsys says the big firms are pushing designers into using complete design flows
DATE: Optimising power in IC design
Power – too much of it – is a recurring theme at this year’s DATE show in Munich