EDA and IP

The 28nm node has created a ‘twilight zone’ for mixed signal designers, says Ravi Subramanian, CEO of Berkeley Design Automation (BDA).

Emulators are changing the economics of semiconductor and full system design, according to Wally Rhines, CEO of Mentor Graphics

Called Vivado, it is a complete SoC design suite including IP and system-level design tools, different from what the FPGA supplier has offered before

Apache, the power analysis EDA specialist which was recently taken over by Ansys, is now looking outside IC design to chip packaging optimization.

“Open source has already reduced barriers to entry for modeling tools,” said Stephen Mellor, originator of the modeling methodology that underlies BridgePoint xtUML

Image processing firm Cambridge Pixel has announced a tool kit for adding radar data to Windows-based commercial ship displays. Called SPx-ECDIS, the kit is for ECDIS (electronic chart display and information systems), and allows the adding of...

For testing complex chip designs it makes sense to combine the two most common test methodologies -logic built-in self-test (LBIST) and automatic test pattern generation (ATPG), writes Amer Guettaf

Mark Walker discusses the evolution of the DO-178 standard alongside the emergence of model-based design and formal methods tools

Verifying a complex FPGA design under DO-254 guidelines for use in safety- and mission-critical airborne systems is challenging and in-hardware verification methodology can help

OpenCL is a parallel computing framework for programming heterogeneous systems containing devices such as multi-core processors, graphics processing units, or Cell Broadband Engine processors