EDA and IP

Esperanto Technologies will present at the RISC-V Workshop in Barcelona next week, (May 7-10) potential changes to high-performance RISC-V processors intended to eliminate speculation-based timing attacks, such as Spectre and Meltdown.  The California-based developer of RISC-V processors is proposing the use of RISC-V cores which minimise changes to the RISC-V ISA or platform specifications in order to provide security against timing-based ...

Cadence Design Systems has introduced design verification IP for three standard interfaces. These are CoaXPress for high-speed imaging, HyperRAM high-speed memory and the JEDEC Universal Flash Storage (UFS) 3.0 specification.  The three tool sets will be used for IP and system-on-chip (SoC) design verification specifically for automotive devices. The UFS 3.0 specification doubles the throughput bandwidth from 1333MB/s in UFS ...

P2i, the Oxfordshire-based liquid repellent nano-coating firm, has been ranked second in the IP League Table compiled by Metis Partners.  The IP League Table highlights those companies which have significantly invested in their IP in the form of IP creation, IP management policies, R&D activities and IP commercialisation. The company was ranked first in the Trade Secret IP asset class ...

Cadence Design Systems has announced its work with TSMC in 5nm and 7nm+ FinFET chip design for mobile devices.  Cadence said its digital, sign-off and custom/analogue tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for the silicon foundry’s 5nm and 7nm+ processes.  Cadence will presents details of the work with TSMC at the CDNLive EMEA 2018 event ...

The MIPI Alliance, the mobile interface specification body, has released a common data format for transmitting software trace and debug information between a test system and a device, such as a system-on-chip (SoC) or platform.  The MIPI SyS-T specification is publicly available to developers, and an accompanying example implementation library is accessible via GitHub. The aim is to avoid market ...

The UK has ratified the Unified Patent Court Agreement (UPCA). UK ratification brings the international court one step closer to reality. The Agreement on the Unified Patent Court (UPC) is an international treaty. The international court will have jurisdiction over patent disputes across its contracting states. It will deliver a single judgment in cross-border disputes between private parties over patents ...

The 55th Design Automation Conference (DAC) programme reflects the changes in the design industry, with artificial intelligence (AI), machine learning, the IoT, storage and security listed as conference topics, alongside the more ‘traditional’ EDA, IP and embedded system design sessions. Alongside EDA companies, Cadence Design Systems, Siemens’ Mentor Graphics and Synopsys, will be NEC, IBM, Amazon Web Services, Alibaba Cloud ...

EnSilica, the Wokingham mixed signal SoC designer has become an ARM Approved Design Partner. “Becoming an Arm Approved Design Partner is an important recognition of our design skills and commitment to quality,” said Ian Lankshear, EnSilica’s MD, “existing customers know that they can trust us with their designs and this third party validation of our abilities will bring in new customers.” ...

Mentor is partnering with SamacSys to provide PCB symbols, footprints and 3D models from within PartQuest

The Electronic Design System Design (ESD) Alliance reports increases in industry revenue from Q3 2016 to Q4 2017, and eight consecutive years of growth. Overall industry revenue increased 10.7% to $2218.6m in Q4 2017, from Q4 2016’s $2455m. The highest growth was in the Americas, where revenues increased 19.5% in the period, followed by Asia-Pacific region which saw 7.8% growth to ...