Denso licenses Cortex-R52 to automated driving

The core allows high functional safety levels (ASIL D) to be achieved, providing hardware-enforced separation of software tasks to ensure safety-critical code is isolated – which decreases the amount of code that needs to be safety-certified.

Denso used ARM ‘cycle models’ – computational models compiled from processor RTL for pre-SoC evaluation – to evaluate the processor’s capabilities ahead of its selection.

“Partnering with ARM gives us access to its ecosystem,” said Denso project manager Hideki Sugimoto. “We evaluated the Cortex-R52 and concluded that the processor’s functional safety capabilities were an excellent match for future automotive applications. Denso, along with our newly established subsidiary NSITEXE, will now work to further enhance these solutions.”

Cortex-R52 has more performance than the Cortex-R5 and is the first ARM v8-R processor, introducing support for a hypervisor, which simplifys the separation of safety-critical code.

The inclusion of Neon SIMD (single instruction multiple data) extensions adds parallel calculation for improved signal processing. It also supports Thumb-2 and DSP instructions as well as foating point as single or double precision.

Inside is an eight-stage pipeline with instruction pre-fetch, branch prediction, superscalar in order execution, parallel execution paths for load-store, MAC, shift-ALU, divide and floating-point.

It has hardware divider and is binary compatible with Arm9, Arm11, Cortex-R4, Cortex-R5, Cortex-R7 and Cortex-R8 embedded processors. Arrangements up to quad-core are supported within a cluster.