EDA and IP

Moortec, the Plymouth developer of on-chip monitoring and analytics IP, is opening a new design centre in Bristol. It is Moortec’s  third design office after Plymouth and Poland. “We’ve a very successful Design office in Poland and our main Head Office in Plymouth – our new additional Design office located in the heart of Bristol will really add to our ...

Designers that want to use Infinera InP open foundry services, part of the Infinera Optical Innovation Center, will benefit from a design workflow that starts from a graphical photonic IC design and system simulation environment. The workflow is enabled by VPItoolkit PDK Infinera— a pluggable toolkit extension to VPI Photonic Circuits – which adds by support of the PDK building blocks for the InP-based PIC foundry process ...

Mentor is addressing the functional safety requirements of ICs in autonomous vehicles with an initiative called ‘Tessent Safety Ecosystem’ which links the firm’s own functional safety tools, including those acquired when it bought Austemper, to those from external partners – notably Arm through its Functional Safety Partnership Program. At the same time, it announced a related tool – for adding fast ...

An Israeli company, Optima Design Automation has introduced two tools for automotive design. The Optima Safety platform consists of Optima-HE and Optima-SE, both based on the company’s Fault Injection Engine (FIE) and designed for fault analysis, targeting safety analysis fault injection for SoC design. The FIE uses parallel simulation and formal verification, rather than fault simulation, and introduces fault list ...

Huawei topped the patent application table last year according to WIPO, the World Intellectual Property Organisation. But Tokyo analysts Patent Result says that only 21% of the 5,405 patent applications made by Huawei last year could be regarded as highly innovative, reports the Nikkei. Patent Result asseses patents by a number of criteria including originality, actual technological applications and versatility ...

Renesas Electronics Corporation has announced expanded access to its IP license portfolio. Customers will gain access to IPs such as 7nm SRAM and TCAM, and standard Ethernet time-sensitive networking. Renesas is working on providing a system IP which includes processing-in-memory. These are suggested to help customers with projects like next-gen AI chips or ASICs for 5G networks. Customers developing custom ...

SiFive has added a ‘micro instruction cache’ option to its Risc-V e2 core – the smallest of its Risc-V intellectual property offerings. Introduced in release 19.05, the micro instruction cache (see μ$ for cache in diagram) sits between the instruction fetch port and the memory system, and offers a speed-up in execution when operating from slower memories such as NVM ...

The Autonomous Vehicle Computing Consortium (AVCC), launched at Arm TechCon in San Jose, brings together Arm, Bosch, Continental, DENSO, General Motors, NVIDIA, NXP Semiconductors and Toyota to help solve some of the challenges to deploy self-driving vehicles. The first is to develop a set of recommendations of a system architecture and a computing platform that reconciles the performance requirements of autonomous ...

Announced at Arm TechConArm, Custom Instructions are a new feature for the Armv8-M architecture.

UltraSoC has announced hardware-based cybersecurity intellectual property products for SoCs at Arm TechCon in San Jose. According to Cambridge-based UltraSoC, they can be used to detect, block and record cyber-attacks, as well as preventing their propagation, in vehicles, factory robots and consumer devices, amongst other applications. “The first product in the range, the UltraSoC Bus Sentinel, allows SoC designers to control ...