Aprisa physical design software upgraded

Improvements include:

• Average full-flow runtime reduction of 30% compared to the previous
release, and up to 2X faster runtimes for larger, more challenging designs.

• Enhancements to all major place-and-route engines, from placement
optimization to clock tree synthesis (CTS) optimization, route optimization and timing analysis. The benefits of these performance enhancements can be observed on almost all IC designs, and especially on large designs with complicated multi-corner multi-mode (MCMM) features. On these designs, Aprisa has proven to run up to 2X faster than the previous generation.

• Up to 60% memory footprint reduction; Aprisa has reduced, on average, 30 percent full-flow peak memory usage for large designs, and up to 60 percent for complex designs, compared to the previous generation. This greater efficiency enables even larger designs with complicated MCMM to be completed on servers with less available RAM.

• 6nm/5nm/4nm design enablement. Siemens has collaborated closely with leading foundries to enable Aprisa for advanced nodes. Aprisa is fully certified for 6nm processes, and Siemens has implemented all required design rules and features for the design enablement of 5nm and 4nm nodes. Final certifications, in collaboration with the world’s leading foundry partners, are in progress.

• Extended support for multi-power domain (MPD). The extended functionalities greatly increase the flexibility and completeness of MPD support, which is critical for extreme low-power designs.