Cadence: IC design tool speeds sign-off

Called Certus closure solution, the “environment automates and accelerates the complete design closure cycle, from sign-off optimisation through routing, static timing analysis and extraction”, said Cadence. “The solution supports the largest chip design projects with unlimited capacity.”

It lists these attributes:

• Distributed hierarchical optimisation and sign-off architecture for cloud and internal data centre environments
• Incremental sign-off allows restore and replacement of only the changed portions of the design
• Automated flow
• Interactive GUI (SmartHub interface) allows cross-probing for detailed timing debug
• Integrated with Integrity 3D-IC for closing inter-die paths between heterogenous die

“Prior to the introduction of the Certus closure solution, a full-chip closure flow involved manual processes from full chip assembly, static timing analysis, and optimisation and sign-off with 100s of views,” according to the company. “The new solution provides a fully automated environment that is massively distributed for superior optimisation and sign-off. This allows concurrent, full-chip optimisation through an engine shared with the Innovus implementation system and the Tempus timing sign-off solution.”

The Certus product age can be found here