LPDDR5X interface IP works up to 8.55Gbit/s

Cadence Design Systems has announced LPDDR5X memory interface intellectual property designed to operate at 8,533Mbit/s, claiming it to be the first.

Based on its LPDDR5 and GDDR6 products, the IP has a PHY and a controller, designed to follow the JEDEC JESD209-5B standard. The controller-PHY interface is based on the latest DFI 5.1 specification, and a variety of on-chip buses are supported, it said.

“LPDDR5X memory opens up high-bandwidth applications beyond the mobile market traditionally served by LPDDR memory, including driver assistance systems, autonomous driving, lower-end edge AI and networking,” according to the company.

For verification, Cadence is offering tools that span IP to system-level verification with DFI verification IP, and LPDDR5X memory model and a system performance analyser.

For more information on this LPDDR5X IP, click here

Photo: Cadence LPDDR5 silicon testing