ISSCC 2023: GaN and Si combine to drive SiC at 1,700V

However, the field is relatively new and the ‘right’ way to drive such devices has yet to be established.

At ISSCC 2023, National Yang Ming Chiao Tung University of Taiwan presented its version of an isolated high and low-side gate drive for 1,700V SiC mosfets, using co-packaged silicon and gallium nitride die, linked by pairs of high-voltage capacitors. Its propagation delay is a mere 7ns.

A capacitive drive needs modulation on the transmit side and demodulation on the receive side, and needs to be able to resist transients from the mosfet side – which can reach >100kV/μs and >10kA/μs, according to the ISSCC presentation – that push common-mode energy bursts back through the twin capacitors, potentially disrupting data transmission.

Innovation in the driver starts with the capacitors (left), which give the driver a 20kV isolation rating.

Each of the two differential capacitors in the isolated paths is actually two capacitors connected in series by a bond wire: one formed within the top metal layers of the silicon transmit chip and one in the top layers of the GaN-on-SoI receive chip. Each has a thick (20μm) top oxide layer under the final metallisation to give the capacitors a high voltage rating.

Modulation at the transmit end is on-off keying of complementary 1.6GHz signals.

At the far end of the capacitive link, a transimpedance amplifier receives the currents and a fast comparator decodes the PWM signal.

To reduce signal disruption due to common-mode transients going back through the capacitor, active transient detectors in the transimpedance amplifier trigger balancing currents to counter the effect of the transient on the amplifier. The result is, at 25°C, immunity up to 260kV/μs for positive transients and 200kV/μs for negative, rising to 282kV/μs and 211kVμs at 225°C, respectively.

The active components throughout the GaN ICs are all hemts, so no complementary circuits are possible. Instead, all the circuits are active load types, with differential circuits used extensively, built from a combination of three transistor types: 12V and 30V enhancement hemts, and a 12V depletion-mode hemt.

Level sifters have been designed from these transistors to convert the comparator outputs into signals that can span from the top of the high-side bootstrap, to the bottom of the negative Vee voltage needed to turn SiC mosfets off fully when they are switching fast.

Rather than needing an external negative supply for Vee, a charge pump is built into the level shifter that generates a local cycle-by-cycle negative voltage with timing to suit the output stage.

To guide the SiC mosfets through their Miller plateaus, three different drive currents are available to drive the gates, actively switched by monitoring the gate waveform at high speed.

National Yang Ming Chiao Tung University worked with Chip-GaN Power Semiconductor and Realtek Semiconductor.

ISSCC 2023 paper 20.1 A high common-mode transient immunity GaN-on-SoI gate driver for high dV/dt SiC power switch.

Diagrams above are copied from paper 20.1 in the ISSCC 2023 Digest of papers.

The IEEE International Solid-State Circuits Conference, held annually in San Francisco, is a (and arguably ‘the’) world showcase for IC-based analogue, digital and RF circuity. It offers an opportunity for IC and circuit design engineers to maintain technical currency, and to network with experts.