TrekApp tool tests stress in SoC and processor designs

Verification and stimulus specialist, Breker Verification Systems, has taken its Cache Coherency TrekApp as the basis for the System Coherency Synthesis TrekApp, which it introduced at DAC58 in San Francisco. The tool uses abstract models of common and novel algorithms to automatically generate high coverage coherency tests for complex, multi-agent system platforms based on coverage directives. The TrekApp can be configured for Arm, RISC-V and other processor configurations, together with a range of storage and I/O architectures.

TrekApp uses the company’s Test Suite Synthesis technology to address coherency across the entire system to include fabric and I/O issues as well as advanced memory architectures more effectively than zero abstraction templating and similar schemes. The company says its the technology reduces test composition time and improve coverage compared to manual tests and basic test generators, including templating schemes.

The TrekApp leverages established methods such as the Dekker algorithm, the Moesi state protocol for system-wide testing, stride testing, false sharing analysis and other exclusive test mechanisms.

The TrekApp generates test content for most SoCs in development today, with a range of processor integration tests for Arm v8/v9 and the RISC-V instruction set architecture (ISA). Specialised custom instructions or complete instruction sets can be included and alternative test algorithms can be inserted, crossing test content output results for high verification coverage.

The System Coherency TrekApp generates C code and transactions for system-level testbenches or UVM (Universal Verification Methodology) sequences for cache unit and sub-system simulation. It operates on virtual prototype platforms, simulation, emulation, FPGA prototyping or final silicon and enables the full debug and profiling of the device under test on those platforms.

This latest TrekApp is a component of the company’s TrekApp library which provides automated test content for a variety of SoC scenarios, including cache coherency, Arm and RISC-V integration, power domain management, security and network traffic generation. TrekApps operate on the company’s Test Suite Synthesis Solution and Synthesizable VerificationOS for automated, coverage-driven test generation for a variety of multi-threaded platforms from a single specification model.

System Coherency Synthesis TrekApp is available now. Pricing is available upon request.

Breker provides advanced test content synthesis solutions for SoC, UVM and post-silicon verification environments.