Tag Archives: SiFive

Qualcomm is to create RISC-V based silicon for wearables, working with Google to optimise it for Google’s Wear OS. “We are excited to extend our work with Qualcomm Technologies and bring a RISC-V wearable solution to market,” said Google general manager Bjorn Kilburn. Leading up to this, the companies will continue to invest in Snapdragon Wear platforms for the Wear ...

SiFive has announced a pair of high-end RISC-V cores for AI and machine learning in consumer, automotive and infrastructure markets. “Performance P870 and Intelligence X390 offer a new level of low power compute density and vector compute capability, and when combined provide performance for data intensive compute,” according to the company, which is advocating combining the general-purpose scalar P870 with ...

SiFive has announced two high-performance RISC-V processing cores. “P670 and P470 are specifically designed for the most demanding workloads for wearables and other advanced consumer applications,” said SiFive v-p Chris Jones. “We have optimised these RISC-V Vector-enabled products to deliver performance and efficiency improvements and we are in evaluations with a number of top-tier customers.” Both are also available in ...

IAR Systems is aiming at SiFive’s E6-A and S7-A automotive RISC-V cores with its latest iteration of Embedded Workbench. “E6-A series is aimed at a variety of real-time 32bit applications, from system control to hardware security modules, safety islands and stand-alone in microcontrollers,” according to IAR. “S7-A is a 64bit, high-performance real-time core suited to the needs of modern SoCs ...

IC intellectual property company SiFive has licensed Segger’s emRun++ C++ library for Risc-V, a library optimised for GCC/LLVM-based tool chains and embedded systems, based on the emRun and emFloat runtime and floating-point libraries. This follows on from last year, when SiFive licensed Segger’s emRun C runtime library for use in its Risc-V IDE and Tool packages. “It was an easy ...

SiFive has opened a  UK R&D centre in Cambridge. The company plans to hire over 100 people. “As part of our global expansion, we’re proud to open our UK R&D Centre in Cambridge to access the considerable local technical talent, especially CPU experts,” said Patrick Little, CEO and Chairman, SiFive, “with long-term plans to grow talent and teams in Cambridge and ...

SiFive has created what “is expected to be the fastest licensable RISC-V processor IP core in the market”, when it emerges in 2022. Building on the earlier Performance P550 processor, company engineering estimates are that it will have 40% more performance per clock cycle  – to 11+SPECInt2006/GHz – and it has architecture enhancements improve maximum clock frequency – together adding ...

SiFive has briefly pulled back the curtains on its most powerful Risc-V processor yet. So far only called ‘Next Generation Core’ or Next-Gen, its official name, final design specs and availability will be unveiled early in December at the Risc-V Summit. The headline figure is that it will improve on the P550’s performance, currently SiFive’s most powerful processor, by 50%. P550 is ...

Risc-V intellectual property creator SiFive has qualified models for its core portfolio from Oxford-based Imperas Software – as well as signing a distribution deal with Valtrix. Imperas’ models for SiFive processor IP are an instruction accurate programmer’s representation with full functionality including user, privileged, system and debug modes, plus configuration options for Risc-V vector extensions and custom instructions. “The models deliver ...

SiFive has announced its highest performance implementation of a Risc-V core yet. Called the Performance P550, the intellectual property is said to deliver a SPECInt 2006 score of 8.65/GHz, “making it the highest performance Risc-V processor available today, and comparable to existing proprietary solutions in the application processor space” according to the company. April 2024 update: SiFive releases a quad ...