Memory

Fujitsu is sampling a Quad SPI FRAM. By using four bi-directional I/O pins, the  device can reach a data transfer rate of 54MByte/s at an operating frequency of 108MHz. Called MB85RQ4ML, it is over four times as fast as Fujitsu’s existing parallel 4Mbit FRAM device and outperforms the 45ns parallel SRAM, the company says. MB85RQ4ML is offered in an SOP-16 package – ...

sureCore, the Sheffield  SRAM IP specialist, today announced the immediate availability of its 28nm FDSOI memory compiler. The compiler supports the company’s low power, single port SRAM IP and dual port SRAM IP for 28nm FDSOI process technology. It offers capacities up to 1Mbit with word lengths up to 288bits and supports 4, 8 and 16 Mux factors. According to the ...

Toshiba has launched 15nm embedded NAND flash for automotive infotainment systems and industrial applications. The technology supports an operating temperature range of -40oC to 85oC and meets AEC-Q100 specifications as well as adhering to PPAP requirements. They come in an 11.5mm x 13mm package that is compliant with the latest JEDEC eMMC standard. Densities range from 8GB to 64GB. Each ...

Cypress Semiconductor has introduced a 64Mbit NOR flash memory device with its highest read bandwidth and fastest program time for a memory chip qualified for automotive designs. The FS-S NOR flash device has a Quad SPI interface and has an 80MHz Double Data Rate (DDR) mode to deliver read bandwidth of 80Mbyte/s. The device provides a 0.475-ms program time per ...

Renesas Electronics says it has developed a dual-port on-chip static random access memory (SRAM) on a 16nm process. The embedded SRAM has been developed for use as video buffer memory in automotive applications such as real-time image processing capabilities necessary for future autonomous-driving vehicle technologies. “When testing the new SRAM in a 16nm process, it achieved both 688ps high-speed operation under the ...

A stacked memory device which has the potential to achieve memory access speeds 14 times faster than today’s DDR4 has been demonstrated by eSilicon, Northwest Logic and SK Hynix. The stacked memory device is complaint with the JEDEC 2.5D packaging standard known as high bandwidth memory (HBM). The chip uses an FPGA-based controller core and PHY for the HBM standard architecture implemented in a Hynix ...

Intel has given an indication at Intel Developer Forum (IDF) in San Francisco this week when the transistor-less 3D XPoint non-volatile memory technology it has been developing with Micron, will appear in commercial products. A range of solid state drives (SSDs) which implement the 3D memory technology will be introduced in 2016. Intel has also given the non-volatile memory a ...

Samsung says it has begun mass production of 48-layer three-bit-per-cell 256Gbit V-NAND. Last week Toshiba said it was beginning pilot production of a 48-layer 256Gbit 3 bit-per-cell V-NAND, which it calls BiCS Flash. In March, Intel/Micron said they were starting to ship a 32-layer V-NAND using floating point flash technology which delivered a 256Gbit memory. Since then Intel/Micron have also ...

Cypress Semiconductor has seen early benefits of its $5bn merger with Spansion with a new 256Mbit memory device added to the Spansion NOR HyperFlash product line. HyperFlash is a high speed memory architecture which can achieve double-data-rate (DDR) read bandwidths as high as 333Mbyte/s for 1.8V products. It is intended to provide a migration path from Quad SPI to dual Quad SPI ...

Diablo Technologies’ Memory1, an all-flash server system memory technology, puts 4TBytes of memory in slots that currently hold 128Gbytes or 384Gbytes, the company said. By delivering greater capability on fewer servers it claims to reduce data centre costs by up to 70%. Memory1 is shipping now to select customers and will be more widely available later in the year. “Memory1 represents a ...