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It is intended particularly at the fastest parallel and serial links, such as DDR4 and 112Gbit/s – the latter achieved using PAM4 four-voltage-level signalling.
“Chips are getting much faster,” Cadence product director Brad Griffin told Electronics Weekly. “There are no shortcuts with 112G with PAM4, everything has to be modelled, and you have to have accurate models.”
The Clarity approach to this is what Griffin describes as ‘true 3D’ – rather than 2D, 2.5D, quasi-static, or any of the other methods used to shrink computational load.
Real measurement from PAM4 silicon (left) compared with modelled output (right)
And to spread the necessary high processing load across sufficient processing cores to get the job done in a reasonable time, the company has created an automated technique.
“With legacy techniques, you need a copy of the whole design on each machine, so you are really going to need 1Tbyte machines,” according to Griffin. “With Clarity, the whole thing will run on whatever resources you have. You don’t have to chop up problem to avoid crashing, so you don’t need an expert to carve up the design so it runs. You can get by with 64Gbyte or 128Gbyte in each of 10 machines and you will not will not run out of memory and you will get a solution.” At the other end of the scale, “we have run it on up to 320CPUs internally, and we have done up to 400 multiple times, and could go to thousands of cores, which we will be doing”, he added.
Exactly how the adaptive meshing massively parallel matrix solver spreads the processing load around, Griffin was not saying, but it came out of the firm’s System Analysis Group, formed 10 months ago, and its workings are related to the way the firm’s Voltus product works.
“Not every line of code is new, there is stuff from other Cadence lines,” he said. “It is not the Voltus solver, but the parallelism techniques are consistent with the Voltus solver,” adding: “We invented it, no one has caught up yet.”
Wearable flexi PCB, modelled in the top diagram
Given 100Gbit/s interconnect between servers, the firm is claiming “nearly linear scalability” between the number of cores used and processing speed-up, and no loss of accuracy. “Clarity is way-closer to linear,” than what has gone before, said Griffin.
When in-house customer processing facilities are insufficient, Cadence is now offering a cloud-based number-crunching service called CloudBurst Platform – which was announced yesterday.
Although it runs on third party cloud resources, Cadence will manage all CloudBurst activity, removing the need for customer IT set-up.
With 112G, everything needs to be modelled:
- Redistribution layers within the IC pakage
- IC bumps/balls, near-chip routing, vias and signal return path
- PCB breakout routing, vias, pad stacks, signal return path
- Motherboard connector mechanical structure
- Backplane – 30 layers with back-drilled vias
Clarity can be used within Cadence’ work flows, where changes to the model can be pushed back up the design chain. It can also be used with the flows of other companies, but will less integration.
very interesting and perhaps a bit frightening? I was involved with some EMC work on boards/ECU’s that were incorporating ethernet. It was closer to 10Gb/s rather than 100, and it was a big change for everyone involved in the PCB layout and connector selection. Very educational, but a definite challenge.
Hard to imagine the change in culture and expectations if full 3D modeling is required before getting boards made.
On the other hand, the EMC folks will be very popular. 🙂
Thanks Steve
I wonder if, after some time, folk will get used to designing at such speeds, or if the layout tools will automatically add standard features that will cope with GHz data busses to a first approximation.
The Cadence tool uses s-parameters – so proper rf design at the microscopic level on a digital pcb – who would have thought.
On a separate note, as the flow of young engineers is not as good as it should be over here in the UK, I wonder what industry will do once the knowledgeable EMC folk have retired – possibly ignore it until everything stops working properly?
Mind you, the harmonics of 100GHz must almost be light, so some cardboard might block them…
It does seem like there will be some sort of standards or rules for routing the high speed buses. The transitions at the chips or connectors will be the challenging part, along with effect with nearby traces. Never a dull moment, I imagine!
Like many skills, I think some EMC engineers are “born”, and some develop into EMC engineers. Here in the middle of the US, the University of Missouri at Rolla has a dedicated EMC program. My recent employer did hire one of their EMC grads for our EMC lab. He left after a while… I suspect we were too heavy into the routine of testing and writing reports, and not involved enough with development work.
As long as there are analog and RF engineers, there is the opportunity to turn them towards the EMC side of things and hone their skills. Of course, analog and RF skills are a bit scarce too, so maybe the folks doing high speed digital design are nearly RF engineers too??