CEA-Leti and Intel put 2D materials on 300mm wafers for nano-sheet transistors

The aim of the multi-year project is to develop a way to transfer layers of 2d material, grown on substrates up to 300mm, to a second substrate for transistor building. Intel will supply manufacturing expertise and CEA-Leti has bonding, layer-transfer and characterisation knowledge.

“Due to their growth temperature exceeding 700°C, and growth on preferred substrates, 2D materials can hardly be deposited on a stack as thin layers, so transfer holds the most promise for integrating them,” said CEA-Leti CEO Sebastien Dauvé (photo left).

Sub-nm mosfets

The intention is to build substrates with which to make sub-1nm channel-thickness stacked-nanosheet fets – one of the technologies mooted as a successor to CMOS.

“Molybdenum and tungsten-based transition-metal dichalcogenides are promising candidates to ensure scaling of mosfets,” according to CEA-Leti. “They are suitable for high-performance and low-power platforms due to their good carrier transport and mobility, even for atomically thin layers. In addition, their device body thickness and moderate energy bandgap lead to enhanced electrostatic control and, thus, to low off-state currents.”

“2D TMD material is a promising option for extending the limits of transistor scaling in the future,” said Intel’s European director of research Robert Chau (photo right).

Founded in 1967, CEA-Leti is a world-leading semiconductor research lab with 1,900 staff in Grenoble. It has offices in Silicon Valley and Tokyo, and has launched 76 start-ups.