Socionext, TSMC and Arm hook up on 2nm chiplets

Socionext, Arm and TSMC are to develop a power-optimised 32-core CPU chiplet in TSMCʼs 2nm silicon technology, aimed at hyperscale data centre server, 5/6G infrastructure, DPU and edge-of-network markets.

This advanced CPU chiplet proof-of-concept using Arm Neoverse CSS technology is designed for single or multiple instantiations within a single package, along with IO and application-specific custom chiplets to optimize performance for a variety of end applications.

Leveraging CPU chiplets, and customized application-specific chiplets, multiple target applications can be supported. When new chiplets become available, a cost-effective package level upgrade path can be supported.

“There is a growing customer demand for granular compute power,” says Socionext evp Hisato Yoshida, “leveraging silicon re-use to create multiple product platforms enables innovative system architectures. This chiplet complements our customersʼ current SoC designs and provides system architects new degrees of freedom to deliver many platform variants for a product family.”